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HC5503T
Data Sheet June 2004 FN4506.2
Balanced PBX / Key System SLIC, Subscriber Line Interface Circuit
The Intersil HC5503T is a low cost Subscriber Line Interface Circuit (SLIC) that replaces the components of a discrete Transformer Analog circuit design. The monolithic integrated design provides improved performance and system reliability. The HC5503T provides: Current limited DC feed to the subscriber loop, maintains a flat frequency response over the voice band and beyond, has self resetting thermal protection that allows conversation to continue while the fault is present, provides a TTL subscriber off hook indication even in the presence of longitudinal currents, and limits system power consumption on short loops. The HC5503T provides balanced 2-wire transmission and has excellent longitudinal balance, while providing on hook transmission and longitudinal current rejection in both the on-hook or off-hook conditions. The SLIC needs only one +5V supply in addition to the main battery supply for loop current and operates over a range of battery voltages (-24V to -58V). Available in 24SO packaging. The HC5503T is ideally suited as a replacement for discrete line circuits in low cost analog PABXs, small Office/Home Office products or Small Key Systems.
Features
* Monolithic Integrated Device * Controlled Supply of Battery Feed Current for Short Loops (30mA) * Single +5V Supply * Allows Interfacing With All Ringing Systems * Switch Hook Detection * Compatible With Worldwide PBX Performance Requirements * Low Power Consumption During Standby * Pb-free Available
Applications
* PBX Switches (Analog, Digital or ISDN) * Key Telephone Systems (KTS) * ISDN PC Plug in Modems * ISDN Small Office/Home Office (SOHO) Terminal Adapters (TA) * CTI (Computer Telephony Integration) Products
Ordering Information
PART NUMBER TEMP. RANGE (C) 0 to 75 0 to 75 0 to 75 PACKAGE 24 Ld SOIC PKG. DWG. # M24.3
Block Diagram
BGND TIP RING C1
HC5503TCB HC5503TCBZ (Note) HC5503TCBZ96 (Note)
24 Ld SOIC (Pb-free) M24.3 24 Ld SOIC M24.3 Tape & Reel (Pb-free)
TF RF LOOP FEED SPEECH CIRCUIT
TX RX
VBAT
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
LOOP DETECTOR SHD
BIAS
RS
VCC
AGND
DGND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1996, Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HC5503T
Absolute Maximum Ratings (Note 1)
Maximum Continuous Supply Voltages (VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V (VCC - VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V Relay Drive Voltage (VRD). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HC-5503T-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Positive Supply Voltage (VCC). . . . . . . . . . . . . . . . . . 4.75V to 5.25V Negative Supply Voltage (VBAT) . . . . . . . . . . . . . . . . . . -24V to -58V High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Off Hook IB+ Off Hook IBOff Hook Loop Current Off Hook Loop Current Off Hook Loop Current Switch Hook Detection Threshold
Unless Otherwise Specified, VBAT = -48V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters TA = 25C. Min-Max Parameters are Over Operating Temperature Range CONDITIONS RL = 600, TA = 25C RL = 600 RL = 1200 RL = 1200, VBAT = -42V, TA = 25C RL = 200 SHD = VOL SHD = VOH MIN 17.5 25.5 10 0 1VRMS 200Hz - 3400Hz, (Note 3) IEEE Method 0C TA 75C TYP 21 30 MAX 5.3 39 34.5 5 5 UNITS mA mA mA mA mA mA mA s
Dial Pulse Distortion Longitudinal Balance 2-Wire Off Hook 2-Wire On Hook Tip and Ring to TX, Off Hook Insertion Loss 2-Wire to TX, RX to 2-Wire Frequency Response Idle Channel Noise 2-Wire to TX, RX to 2-Wire 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level (Note 3) (Note 3) At 1kHz, 0dBm Input Level, Referenced 600
-
65 63 58 0.05 0.02
0.2 0.05
dB dB dB dB dB
-
1 -89 40 -
5 -85 -
dBrnC dBm0p dB VPEAK
Trans Hybrid Loss, RX to TX Overload Level, 2-Wire to TX, RX to 2-Wire
Balance Network Set Up for 600 Termination at 1kHz VCC = +5V, (Note 3)
2.5
2
HC5503T
Electrical Specifications
PARAMETER Level Linearity 2-Wire to TX, RX to 2-Wire Unless Otherwise Specified, VBAT = -48V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters TA = 25C. Min-Max Parameters are Over Operating Temperature Range (Continued) CONDITIONS At 1kHz, (Note 3) Referenced to 0dBm Level +3 to -40dBm -40 to -50dBm -50 to -55dBm Power Supply Rejection Ratio VCC to 2-Wire VCC to Transmit VBAT to 2-Wire VBAT to Transmit Logic Input Current (RS, RC) Logic Inputs (RS, RC) Logic `0' VIL Logic `1' VIH Logic Output (SHD) Logic `0' VOL Logic `1' VOH NOTE: 3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. ILOAD 800A, VCC = 5V ILOAD 40A, VCC = 5V 2.7 0.1 0.5 5.0 V V 2.0 0.8 5.5 V V 0V VIN 5V (Note 3) 200 - 3400kHz, RL = 600 40 40 40 40 100 dB dB dB dB A 0.05 0.1 0.3 dB dB dB MIN TYP MAX UNITS
Pinout
HC5503T (SOIC) TOP VIEW
TIP RING VCC N/C C1 DGND RS N/C TF 1 2 3 4 5 6 7 8 9 24 TX 23 AGND 22 N/C 21 RX 20 T3 19 T2 18 T1 17 N/C 16 N/C 15 N/C 14 N/C 13 SHD
RF 10 VBAT 11 BGND 12
3
HC5503T Pin Descriptions
24 PIN SOIC 1 SYMBOL TIP DESCRIPTION An analog input connected to the TIP (more positive) side of the subscriber loop through a 150 feed resistor. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring purposes. An analog input connected to the RING (more negative) side of the subscriber loop through a 150 feed resistor. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. Positive Voltage Source - Most positive supply. VCC is typically 5V. No Connect. For proper operation this pin should be left floating. Capacitor - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the voice band hybrid. Typical value is 0.3F, 30V. Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC microcircuit. This pin should be tied to 5V. No Connect. For proper operation this pin should be left floating. Tip Feed - A low impedance analog output connected to the TIP terminal through a 150 feed resistor. Provides voice signals to the telephone set and sink longitudinal current. Ring Feed - A low impedance analog output connected to the RING terminal through a 150 feed resistor. Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. Negative Voltage Source - Most negative supply. VBAT has an operational range of -24V to -58V. Frequently referred to as "battery". Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop currents exceeding 10mA and disabled for loop currents less than 5mA. No Connect. For proper operation this pin should be left floating. No Connect. For proper operation this pin should be left floating. No Connect. For proper operation this pin should be left floating. No Connect. For proper operation this pin should be left floating. Used during production testing. For proper operation this pin should be connected to pin T2. Used during production testing. For proper operation this pin should be connected to pin T1. Used during production testing. For proper operation this pin should be connected to Analog Ground pin AGND. Receive Input - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed terminals, which in turn drive tip and ring through 300 of feed resistance on each side of the line. No Connect. For proper operation this pin should be left floating. Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. Transmit Output - A low impedance analog output which represents the differential voltage across Tip and Ring. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
RING VCC N/C C1 DGND RS N/C TF RF VBAT BGND SHD N/C N/C N/C N/C T1 T2 T3 RX
22 23 24
N/C AGND TX
NOTE: All grounds (AGND, BGND, and DGND) must be applied before VCC or VBAT. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first.
4
HC5503T Applications Diagram
SYSTEM CONTROLLER 13 5V 7 RS SHD TX TIP K1A RB1 RB2 (NOTE 4) PRIMARY SUBSCRIBER PROTECTION LOOP 1 9 TIP TIP FEED RX SLIC HC5503T T3 VBAT 10 RB4 K1A RING RB3 2 RING VBAT 11 BGND DGND AGND C2 12 6 23 C1 VCC C3 3 T2 T1 C5 24
21
C4
20 19 18 5 C1
RING FEED
PTC -48V VCC PIN NUMBERS GIVEN FOR SOIC PACKAGE. RING GENERATOR -48V
Z1
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C1 = 0.3F, 30V, 20%. C2 = 0.01F, 100V, 20%. C3 = 0.01F, 20V, 20%. C4 = 0.5F, 20V, 20%. C5 = 0.5F, 30V, 20%. RB1 = RB2 = RB3 = RB4 = 150. PTC used as ring generator ballast.
NOTES: 4. Secondary protection diode bridge recommended is a 2A, 200V type. 5. All grounds (AG, BG, and DG) must be applied before VCC or VBAT. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. 6. Application shows Ring Injected Ringing.
5
HC5503T Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 6

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